1. Field of the Invention
The invention relates to the layout of a semiconductor memory, particularly relates to the layout of a dynamic random access memory (DRAM) comprising a memory cell array in which memory cells are arranged in a matrix shape and a sense amplifier array which is disposed adjacent to the memory cell array.
2. Description of the Related Art
In recent years, a DRAM is required to operate increasingly at high speed. Various propositions have been put forth to realize this requirement.
For example, there is a proposition that wirings each having resistance lower than that of word lines are arranged adjacent to the word lines, and the word lines and the wirings having low resistance (hereinafter referred to as low resistance wirings) are connected to one another in word line shunt areas provided at given intervals, so that signals applied to the word lines are transmitted at high speed.
Japanese Patent Laid Open Publication No. 9-139477 published May 27, 1997 has put forth a proposition of the layout of word line shunt areas in a memory cell array in the interests of high speed operation.
If a desired word line is selected out of a plurality of word lines in a memory cell array, data in the memory cell connected to the selected word line is applied to a bit line. Data applied to the bit line is amplified by a given sense amplifier of a plurality of sense amplifiers in a sense amplifier array disposed adjacent to the memory cell array. The amplified data is applied to a data bus which is arranged in the sense amplifier array.
Considering the delay of a signal applied to the word line, a plurality of word line shunt areas are arranged in predetermined positions in the memory cell array. Such a delay of signal applied to the word line has received widespread attention.
However, the delay of a control signal for controlling a plurality of sense amplifiers has not received widespread attention so far, and hence no effective proposition has been put forth.
As miniaturization and high capacity of a DRAM have progressed in recent years, a sense amplifier circuit and a method of controlling it becomes complex. Accordingly, a load applied to sense amplifier control signal lines each transmitting a control signal for controlling a plurality of sense amplifiers becomes large. As a result, there occurs a delay of the control signal for controlling the sense amplifiers. It seems that this delay causes a serious problem when miniaturization and high-capacity of a DRAM increasingly progress.